The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnect structures for a security application and methods of forming an interconnect structure for a security application.
An interconnect structure may be formed by back-end-of-line (BEOL) processing and used to provide electrical connections with device structures fabricated on a substrate by front-end-of-line (FEOL) processing. Typical constructions for a BEOL interconnect structure include multiple metallization levels arranged in a stack. The metallization levels of the BEOL interconnect structure may be formed by layer deposition, lithography, etching, and polishing techniques characteristic of damascene processes.
A mechanism for preventing the unauthorized cloning of an integrated circuit is through the use of an on-chip physical unclonable function (PUF), which is a challenge-response mechanism in which the mapping between a challenge and the corresponding response exploits manufacturing process variations inside integrated circuits to impart uniqueness. For example, the PUF may be embodied in active device structures that generate a set of binary bits that can be read as the response.
The correlation among the binary bits generated by the PUF and read from different chips must be random in order to provide security. Nevertheless, the response from the PUF associated with a chip should remain fixed and static over time. However, active device structures are subject to distortion by operating conditions, such as voltage and temperature, and require complicated sensing circuits to initiate the challenge and detect the response.
Improved interconnect structures for a security application and methods of forming an interconnect structure for a security application are needed.